The present invention relates to a semiconductor device including a nonvolatile memory cell and its peripherals, and more particularly, it relates to a flash EEPROM.
Recently, there is increasing demand for a nonvolatile memory that is electrically writable under application of a low voltage. A sense amplifier is one of the important technique of such a low voltage operable nonvolatile memory. A conventional sense amplifier will be herein exemplified.
A circuit diagram for the sense amplifier shown in FIG. 40 will be described first. The sense amplifier receives a control signal SAE and a data line signal DL at its two input terminals, and outputs an output signal OUT through its output terminal.
In this sense amplifier, an inverter INV1 receives the control signal SAE at its input terminal and outputs a signal N1 generated by inverting the control signal SAE. A CMOS inverter including a P-channel MOS transistor Qp1 and an N-channel MOS transistor Qn1 inverts the output signal N1 from the inverter INV1. The output signal N1 from the inverter INV1 is applied to the gates of the transistors Qp1 and Qn1. The source of the P-channel MOS transistor Qp1 is connected to a terminal for supplying a supply voltage VDD, and the source of the N-channel MOS transistor Qn1 is grounded. The drains of the transistors Qp1 and Qn1 are connected to a common signal line, through which a signal N2 generated by inverting the signal N1 is transferred.
P-channel MOS transistors Qp2 and Qp3 receive the output signal N1 from the inverter INV1 at their gates, and N-channel MOS transistors Qn2 and Qn3 receive the output signal N2 from the CMOS inverter at their gates. The sources of the P-channel MOS transistors Qp2 and Qp3 are respectively connected to terminals for supplying a supply voltage VDD, and the sources of the N-channel MOS transistors Qn2 and Qn3 are connected to a common data line (a signal line L1). The drains of the transistors Qp2 and Qn2 are connected to each other, and the drains of the transistors Qp3 and Qn3 are connected to each other. A signal N3 is output through a signal line connecting the transistor Qp3 to the transistor Qn3.
A P-channel MOS transistor Qp4 receives a ground potential at its gate, an N-channel MOS transistor Qn4 receives the signal N3 at its gate, and an N-channel MOS transistor Qn5 receives the control signal SAE at its gate. The source of the transistor Qp4 is connected to a terminal for supplying a supply voltage VDD, and the drain thereof is connected to the drain of the transistor Qn4. The source of the transistor Qn4 is connected to the drain of the transistor Qn5, and the source of the transistor Qn5 is grounded. These three transistors Qp4, Qn4 and Qn5 together serve as an output unit. The output signal OUT of the sense amplifier is output through a signal line connecting the drain of the transistor Qp4 to that of the transistor Qn4.
An N-cannel MOS transistor Qn6 is disposed between the gate of the transistor Qn4 and the ground so as to release charge from the gate of the transistor Qn4. An N-cannel MOS transistor Qn8 is disposed between the gate of the transistor Qn2 and the ground, and the gate of the transistor Qn8 is connected to the data line (the signal line L1). An N-channel MOS transistor Qn7 is disposed between the signal line L1 and the ground, and the gate of the transistor Qn7 is supplied with the output signal N1 from the inverter INV1.
The operation of this sense amplifier will now be described.
When the control signal SAE is at a high level and no current flows from the data line (signal line L1) to the ground, the sense amplifier is operated as follows: Since the output signal N1 of the inverter INV1 is at a low level, the transistor Qp1 of the CMOS inverter is turned off and the transistor Qn1 is turned on, resulting in increasing the potential level of the output signal N2 from the CMOS inverter. This turns on the subsequent transistors Qp2, Qp3, Qn2 and Qn3, but the transistor Qn8 starts to be turned on because the potential level of the data line signal DL is high. Because the transistor Qn8 starts to be turned on, the potential level of the signal N2 is decreased and the transistors Qn2 and Qn3 start to be turned off. As a result, the potential level of the signal N3 becomes high. This makes the gate potential of the transistor Qn4 high, thereby allowing the transistor Qn4 to operate. Thus, an output signal OUT is output at a low level.
When the control signal SAE is at a high level and a current flows from the data line signal DL to the ground, the sense amplifier is operated as follows: Since the potential level of the output signal N2 from the CMOS inverter becomes high as in the aforementioned case, the subsequent transistors Qp2, Qp3, Qn2 and Qn3 are all turned on. Nevertheless, the potential of the data line signal DL becomes low because the memory cell connected to the data line (signal line L1) is in an on state, and the transistor Qn8 is kept in an off state. This results in a high potential level of the signal N2 and a low potential level of the signal N3, thereby turning off the transistor Qn4. Thus, an output signal OUT is output at a high level.
When the control signal SAE is at a low level, all the transistors Qp2, Qp3, Qn2 and Qn3 are turned off, resulting in turning off the transistor Qn5. Therefore, the output unit outputs the output signal OUT at a high level. In this case, since both the transistors Qn6 and Qn7 are on, charge is released to the ground from the gates of the transistors Qn4 and Qn8, resulting in keeping low the gate potential of the transistors Qn4 and Qn8.
For attaining a high speed operation, the sizes of the transistors Qp3 and Qn3 are made small so as to minimize the capacitance of the signal N3. Since the transistors Qp3 and Qn3 are disposed previously to the output unit, the load on the transistor Qn4 in the output unit is decreased. Since the transistors Qp2 and Qn2 are disposed previously to the transistors Qp3 and Qn3, the charge is rapidly supplied to the data line. This increases the operation speed of the circuit together with the operation of the transistor Qn8.
FIG. 41 is a characteristic diagram showing the relationship between a supply voltage VDD and a level sensing current in this sense amplifier. The level sensing current herein indicates a current that flows through the data line when the logical voltage of the output signal OUT of the sense amplifier undergoes a transition, i.e., when the transistor Qn4 is turned on/off. As described above, when a current with a level exceeding a predetermined level flows through the data line, the logical voltage of the output signal OUT undergoes a high transition, and when the current with a level exceeding the predetermined level does not flow through the data line, the logical voltage of the output signal OUT undergoes a low transition. In other words, a memory cell having a memory cell on current exceeding a level sensing current is in a low threshold state, and a memory cell having a memory cell on current not exceeding the level sensing current is in a high threshold state. As is shown with a curve VSALC1 in FIG. 41, the level sensing current increases as the supply voltage VDD increases in the conventional sense amplifier. In addition, the increase of the supply voltage VDD also causes the increase of the increasing ratio of the level sensing current.
FIG. 42 is a characteristic diagram showing the relationship between a supply voltage and a data line voltage. As is shown with a characteristic line VDLC1 in FIG. 42, the data line voltage increases as the supply voltage VDD increases.
FIG. 43 is a characteristic diagram showing the relationship among a supply voltage VDD, a level sensing current and a memory cell current. A curve SALVO shows the variation characteristic of a level sensing current, and a curve MCON0 shows the variation characteristic of a memory cell on current. The memory cell on current herein indicates a characteristic against a supply voltage of a current, which flows between the source and the drain of an FET forming a nonvolatile memory cell when the floating gate is not charged negatively (i.e., in an erasing state). As is shown in FIG. 48, the characteristic curve SALEV0 of the level sensing current has a shape swelling downward similarly to the characteristic curve shown in FIG. 41. The memory cell current generally has a similar characteristic to a current flowing between the source and the drain of a MISFET, and hence, the characteristic curve MCON0 of the memory cell current increases as the supply voltage increases but eventually reaches a saturation state, i.e., has a shape swelling upward.
There exists a memory cell off current (or a memory cell off leak current) in contrast with a memory cell on current. A memory cell off current herein indicates a current that flows through a memory cell when it is not supposed to flow. Such a current is caused in the following two cases: First, when an FET forming a nonvolatile memory cell is negatively charged (i.e., in a writing state), namely, when the threshold value of a memory cell transistor is set to be high, the control gate of the memory cell is selected. In such a case, since the negative charge is insufficient and the threshold value is insufficiently high, a current flows through the memory cell. Secondly, although the control gate of the memory cell is not selected, a current flows through the memory cell because the memory cell transistor is of a depletion mode.
In a sense amplifier, the level sensing current is adjusted to have an intermediate value between the memory cell on current and the memory cell off current by adjusting the threshold values of the transistors.
Furthermore, a flash memory stores a data by setting the threshold value of a memory cell transistor within a predetermined range by charging (for a writing operation) or discharging (for an erasing operation) a floating gate. For example, when two kinds of data are desired to be stored using one memory cell, two kinds of threshold values, "H" and "L", suffice. When three kinds of data are desired to be stored using one memory cell, an intermediate threshold value is required to be set as well as "H" and "L". At this point, it is necessary to confirm whether or not the threshold value has been appropriately set, which operation is designated as verification. The verification is performed as follows:
In the verification of a memory cell in a writing state, i.e., having a high threshold value, it is determined whether or not a current flows through the memory cell using the level sensing current, with the word line of the memory cell selected. When it is determined that the level sensing current does not flow and the sense amplifier outputs an output signal OUT at a low level, it is confirmed that the desired high threshold value has been set in the memory cell.
In the verification of a memory cell in an erasing state, i.e., having a low threshold value, it is also determined whether or not a current flows through the memory cell using the level sensing current, with the word line of the memory cell selected. When it is determined that the level sensing current flows and the sense amplifier outputs an output signal OUT at a high level, it is confirmed that the low threshold value has been set in the memory cell. In the verification of the memory cell in an erasing state, however, it is necessary to further confirm that the level sensing current does not flow when the memory cell is not selected. The reason is as follows: An off leak current can flow through an unselected memory cell if the memory cell is of a depletion mode as described above. A plurality of memory cells are connected to one data line, and during the verification of one memory cell in a writing state, an off leak current can flow through another memory cell that is in an erasing state and is not selected. Such an off leak current can decrease the reliability of the verification.
A semiconductor device including the above-mentioned sense amplifier has the following problems:
First, the sense amplifier has a characteristic that, as the supply voltage VDD increases, the level sensing current increases and in addition the increasing ratio of the level sensing current also increases. This results in that the level sensing current is extremely small when the supply voltage is low. In, for example, a flash EEPROM that stores a data by varying the threshold voltage of a memory cell transistor, a slight current can flow through the memory cell transistor even when the threshold voltage thereof is set to be so high that a current is prevented from flowing therethrough. Accordingly, when the level sensing current is small under application of a low supply voltage as described above, it is difficult to distinguish from a current flowing through a memory cell transistor having a low threshold value from a leak current flowing through a memory cell transistor having a high threshold value, in reading a data from the memory cell. This can cause error discrimination of a data stored in the memory cell by the sense amplifier. Furthermore, when the supply voltage VDD is low, the memory cell on current is decreased, and hence, error discrimination can also be caused. There also arises a problem that a longer time is required for the discrimination by the sense amplifier.
Secondly, the data line voltage increases as the supply voltage increases. In, for example, a flash EEPROM that stores a data by varying the threshold voltage of a memory cell transistor, a current is allowed to flow through the memory cell transistor when a voltage is applied to the gate of the memory cell transistor whose threshold voltage is set to be low. In such a case, a high data line voltage can increase the threshold voltage of the memory cell transistor. The increase of the threshold voltage can decrease the current flowing under application of a voltage to the gate of the memory cell transistor. This also can lead to error discrimination by the sense amplifier as in the aforementioned case.
Thirdly, a value of the level sensing current is univocally defined with regard to one supply voltage value. Therefore, it is impossible to determine with margin included whether or not a memory cell current in an on state is larger than a level sensing current value during verification. Accordingly, in, for example, a flash EEPROM that stores a data by varying the threshold voltage of a memory cell transistor, it is impossible to determine whether or not the memory cell current in the on state has sufficient margin even when the threshold voltage is set to be sufficiently low to allow a current to flow. Furthermore, in such a flash EEPROM, there arises another problem that frequent change of the threshold voltage of the memory cell transistor can cause a failure of the flash EEPROM because the memory cell current in the on state decreases as compared with that in the initial state.
Fourthly, since a value of the level sensing current is univocally defined with regard to one supply voltage value, it is impossible to determine with margin included whether or not a memory cell current in an off state is smaller than a level sensing current value. Therefore, in, for example, a flash EEPROM that stores a data by varying the threshold voltage of a memory cell transistor, a slight off current (a leak current) can flow through the memory cell transistor when the memory cell transistor is turned off by grounding the gate thereof. Such an off current increases at a higher temperature, which can disadvantageously causes error discrimination and a failure in the conventional sense amplifier.